In electrically connecting an integrated circuit chip to a printed circuit board or the like, there are typically two levels of interconnection. In the first level, the integrated circuit chip is connected to a chip package. Common techniques for achieving this first level chip-to-package interconnection include wire bonding, flip-chip processing and lead frame connection. The second level of interconnection provides electrical connection of the chip package to the printed circuit board.
Package designers face serious challenges as the circuit density of a given size integrated circuit chip increases. The circuit density of a particular chip often plays a major role in the number of input/output signal pads on an active surface of a chip. An increase in the input/output count affects a number of factors which must be considered by package designers.
Firstly, a high input/output count requires a correspondingly high interconnection density, with respect to both the first and second levels of interconnection. A dense interconnect scheme is susceptible to electrical shorts. A second factor follows from the first. An integrated circuit chip having a dense interconnect scheme is typically associated with a relatively low manufacturing yield. Thus, a desirable package design is one which allows a high density of electrical paths that can be repeatedly and reliably isolated.
Using wire bonding techniques, the first level of interconnection is achieved by bonding individual bond wires from input/output pads on an integrated circuit chip to contact sites on a chip package. Even with the aid of robotics, the attachment of bond wires to input/output pads and to contact sites is a time consuming process that is susceptible to error The use of lead frames, such as a tape automated bonding lead frame, in which each lead is mechanically coupled to adjacent leads provides an alternative. However, high density lead frames have extremely thin leads that are susceptible to being bent during connection between a chip and a chip package.
It is an object of the present invention to provide a method of packaging an integrated circuit chip having a high density, high yield interconnection scheme.